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MTD2955V Power MOSFET 12 A, 60 V
P-Channel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
Features
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12 A, 60 V RDS(on) = 185 mW (Typ)
* Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature * Pb-Free Packages are Available
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 MW) Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 ms) Total Power Dissipation Derate above 25C Total Power Dissipation @ 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 W) Thermal Resistance - Junction to Case - Junction to Ambient (Note 1) - Junction to Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 12 8.0 42 60 0.4 2.1 -55 to 175 216 Unit Vdc Vdc G
P-Channel D
S Vdc Vpk Adc Apk Watts W/C Watts C mJ 4 DPAK-3 CASE 369D STYLE 2 1 C 2 3 4 12 3
DPAK-3 CASE 369C STYLE 2
TJ, Tstg EAS
C/W RqJC RqJA RqJA TL 2.5 100 71.4 260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. When surface mounted to an FR4 board using the 0.5 sq.in. pad size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 7 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2004
1
April, 2004 - Rev. 7
Publication Order Number: MTD2955V/D
MTD2955V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 6.0 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc, Vdc ) RG = 9.1 W) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 3) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD - - trr (IS = 12 Adc, VGS = 0 Vdc, Adc Vdc dIS/dt = 100 A/ms) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature. Max limit - Typ 5. Reflects typical values. Cpk = 3 x SIGMA LD - - LS - 7.5 - 3.5 4.5 - - nH nH ta tb QRR - - - - 1.8 1.5 115 90 25 0.53 3.0 - - - - - mC ns Vdc - - - - - - - - 15 50 24 39 19 4.0 9.0 7.0 30 100 50 80 30 - - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 550 200 50 770 280 100 pF (Cpk 2.0) (Note 5) VGS(th) 2.0 - (Cpk 1.5) (Note 5) RDS(on) - VDS(on) - - gFS 3.0 - - 5.0 2.9 2.5 - mhos 0.185 0.230 Vdc 2.8 5.0 4.0 - Vdc mV/C W (Cpk 2.0) (Note 5) V(BR)DSS 60 - IDSS - - IGSS - - - - 10 100 100 nAdc - 58 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
Reverse Recovery Time
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MTD2955V
TYPICAL ELECTRICAL CHARACTERISTICS
25 I D , DRAIN CURRENT (AMPS) 24 9V 8V I D , DRAIN CURRENT (AMPS) 21 18 15 12 9 6 3 10 0 2 3 4 5 6 7 8 9 10
TJ = 25C
VGS = 10 V
VDS 10 V
TJ = - 55C 100C 25C
20 7V
15
10
6V
5 0
5V
0
1
2
3
4
5
6
7
8
9
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 3 6 9 15 18 12 ID, DRAIN CURRENT (AMPS) 21 24 25C - 55C VGS = 10 V TJ = 100C
0.250 TJ = 25C VGS = 10 V
0.225 0.200 0.175
0.150
15 V
0.125 0.100 0.075 0.050 0 3 6 9 18 12 15 ID, DRAIN CURRENT (AMPS) 21 24
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 - 50 - 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 VGS = 10 V ID = 6 A I DSS , LEAKAGE (nA)
1000
VGS = 0 V
TJ = 125C 100 100C
10
0
20 50 10 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
60
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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MTD2955V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1800 1600 C, CAPACITANCE (pF) 1400 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Ciss Coss Crss 15 20 25 Crss Ciss VDS = 0 V VGS = 0 V
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
TJ = 25C
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTD2955V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 2 Q3 4 6 8 10 12 14 VDS 16 18 QT, TOTAL CHARGE (nC) Q1 Q2 VGS QT 30 27 24 21 18 15 12 ID = 12 A 9 TJ = 25C 6 3 0 20 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 12 A VGS = 10 V TJ = 25C tr tf
t, TIME (ns)
100
10
td(off) td(on)
1
1
10 RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
12 11 I S , SOURCE CURRENT (AMPS) 10 9 8 7 6 5 4 3 2 1 0 0.5 VGS = 0 V TJ = 25C
0.7
0.9
1.1
1.3
1.5
1.7
1.9
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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MTD2955V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 225 E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) VGS = 15 V SINGLE PULSE TC = 25C 200 175 150 125 100 75 50 25 0 25 50 75 100 125 150 175 ID = 12 A
10 100 ms 1 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms dc
0.1
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t)
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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MTD2955V
ORDERING INFORMATION
Device MTD2955V MTD2955VG MTD2955V-1 MTD2955V-1G MTD2955VT4 MTD2955VT4G Package DPAK-3 DPAK-3 (Pb-Free) DPAK-3 DPAK-3 (Pb-Free) DPAK-3 DPAK-3 (Pb-Free) Shipping 75 Units/Rail 75 Units/Rail 75 Units/Rail 75 Units/Rail 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
DPAK-3 CASE 369C STYLE 2 4 Drain YWW T 2955V
DPAK-3 CASE 369D STYLE 2 4 Drain YWW T 2955V 123 Gate Drain Source 2955V Y WW Device Code = Year = Work Week
2 1 3 Drain Gate Source
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MTD2955V
PACKAGE DIMENSIONS
DPAK-3 CASE 369C-01 ISSUE O
-T- B V R
4
SEATING PLANE
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005) T
DIM A B C D E F G H J K L R S U V Z
M
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MTD2955V
DPAK-3 CASE 369D-01 ISSUE B
B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
Z A
3
S -T-
SEATING PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
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MTD2955V
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MTD2955V/D

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